The following has been known about a conventional liquid crystal display device. An offset voltage which is incidentally produced by, for example, a manufacturing variation in a differential amplifier constituting an output circuit section (output circuit 4408 of FIG. 18) of a display drive circuit (source driver 3802 of FIG. 18) causes a difference from an ideal driving voltage to be supplied to a liquid crystal display element, so that a display image is not suitably displayed, and so-called display unevenness occurs. This causes a deterioration in display quality.
For example, Patent Literature 1 describes a technique for solving display unevenness caused by such an offset voltage. The following description discusses first to third conventional techniques described in Patent Literature 1.
(a) and (b) of FIG. 19 are block diagrams each illustrating an output circuit of a source driver IC in accordance with the first conventional technique, and also illustrating an example of an operation thereof. In (a) and (b) of FIG. 19, only blocks indicated by the respective reference numerals 4405, 4407, and 4408 in FIG. 18 are shown as circuits corresponding to two output terminals.
In (a) and (b) of FIG. 19, the reference numeral 4501 indicates a voltage follower which uses operational amplifiers in an output circuit which drives an odd-numbered output terminal, the reference numeral 4502 indicates a voltage follower which uses, in an output circuit which drives an even-numbered output terminal, operation amplifiers identical to those used in the voltage follower 4501. The reference numerals 4503, 4504, 4505, and 4506 each indicate an output alternation switch for switching a polarity of an output voltage of a liquid crystal drive output. The reference numeral 4507 indicates a D/A conversion circuit which carries out digital/analog conversion with respect to a positive-polarity voltage. The reference numeral 4508 indicates a D/A conversion circuit which carries out digital/analog conversion with respect to a negative-polarity voltage. The reference numerals 4509 and 4510 each indicate a hold memory in which display data is held. The reference numeral 4511 indicates an odd-numbered output terminal, and the reference numeral 4512 indicates an even-numbered output terminal. The reference numeral 4513 in the operational amplifier 4501 and the reference numeral 4514 in the operational amplifier 4502 each indicate an N-channel MOS input operational amplifier. The reference numeral 4515 in the operational amplifier 4501 and the reference numeral 4516 in the operational amplifier 4502 each indicate a P-channel MOS input operational amplifier.
According to the above configuration, the output circuit has two operational amplifiers, which are an operational amplifier that has an N-channel MOS transistor in its input stage and an operational amplifier that has a P-channel transistor in its input stage, are provided so that both a positive-polarity voltage and a negative-polarity voltage can be supplied (full-range supplied) to one output terminal. This makes it possible to cancel deviations A and −A caused by offset voltages in two frames (see FIG. 20).
However, according to the configuration of the first conventional technique, the output circuit has two operational amplifiers per output terminal. This causes a problem of an increase in circuit scale and electric power consumption.
In view of the above, a configuration (see (a) and (b) of FIG. 21) which allows a smaller circuit scale and lower electric power consumption by halving the number of operational amplifiers is taken as an example of the second conventional technique. However, according to the configuration, two operational amplifiers (operational amplifiers 4601 and 4602) each driving one output differ between a case where a positive-polarity voltage is outputted and a case where a negative-polarity voltage is outputted. Therefore, unlike the case of the first conventional technique, it is impossible to cancel offset voltages produced by, for example, a manufacturing variation. This is specifically described below with reference to FIG. 22.
FIG. 22 shows a waveform of a liquid crystal driving voltage in a case where the operational amplifier 4601 has an offset voltage A and the operational amplifier 4602 has an offset voltage B. In FIG. 22, deviations from respective expectation voltages differ between the case where a positive-polarity voltage is outputted and the case where a negative-polarity voltage is outputted. Accordingly, a component (=(A−B)/2) of a difference between the two deviations remains as an error voltage in an average voltage of driving voltages which are to be applied to liquid crystal display pixels. The error voltage, which is incidentally produced for each drive output terminal, causes a difference in applied voltage between pixels of a liquid crystal display device, so that display unevenness occurs.
The third conventional technique (e.g., techniques described in Patent Literatures 1 and 2) is taken as an example of a technique for solving the problems of the first and second conventional techniques.
FIG. 23 shows a configuration example of a differential amplifier circuit in accordance with the third conventional technique. Note that FIG. 23 shows a case where N-channel MOS transistors are used as input transistors.
The reference numerals in FIG. 23 indicate respective members as below. The reference numerals 101 and 102 each indicate an N-channel MOS input transistor. The reference numeral 103 indicates a constant current source that supplies an operational electric current to the differential amplifier circuit. The reference numeral 104 indicates a load resistor (resistance element) of the input transistor 101. The reference numeral 105 indicates a load resistor (resistance element) of the input transistor 102. The reference numerals 106 and 107 each indicate a switch for switching an input signal. The reference numerals 108 and 109 each indicate a switch for switching an output signal. The reference numeral 110 indicates an in-phase input terminal. The reference numeral 111 indicates an antiphase input terminal. The reference numeral 112 indicates an in-phase output terminal. The reference numeral 113 indicates an antiphase output terminal. The reference numeral 114 indicates a switching signal input terminal via which a switching signal for simultaneously switching the switches 106 to 109 is inputted.
The input transistor 101, the load resistor 104, the input transistor 102, and the load resistor 105 constitute an amplifier circuit. The transistors 101 and 102 constitute a differential pair. The switches 106 to 109 are simultaneously controlled by the switching signal 114. Note that the in-phase input terminal 110 corresponds to a + input terminal of the operational amplifier 4601 illustrated in FIG. 21 and that the antiphase input terminal 111 corresponds to a − input terminal of the operational amplifier 4601 illustrated in FIG. 21.
FIG. 24 illustrates a state in which the differential amplifier circuit illustrated in FIG. 23 operates. FIG. 25 illustrates another state in which the differential amplifier circuit illustrated in FIG. 23 operates. The following description discusses, with reference to FIGS. 24 and 25, how the differential amplifier circuit operates.
In the state illustrated in FIG. 24, the in-phase input terminal 110 is connected to a gate of the input transistor 101 via the switch 106. An input signal inputted via the in-phase input terminal 110 is outputted, by a function of the load resistor 104 connected to a drain of the input transistor 101, via the antiphase output terminal 113 as an antiphase output signal after passing through the switch 109. Meanwhile, the antiphase input terminal 111 is connected to a gate of the input transistor 102 via the switch 107. An input signal inputted via the antiphase input terminal 111 is outputted, by a function of the load resistor 105 connected to a drain of the input transistor 102, via the in-phase output terminal 112 as an in-phase output signal after passing through the switch 108. That is, the in-phase input signal is amplified by the input transistor 101 and the load resistor 104, whereas the antiphase input signal is amplified by the input transistor 102 and the load resistor 105.
In contrast, in the state illustrated in FIG. 25, the in-phase input terminal 110 is connected to the gate of the input transistor 102 via the switch 107. An input signal inputted via the in-phase input terminal 110 is outputted, by a function of the load resistor 105 connected to the drain of the input transistor 102, via the antiphase output terminal 113 as an antiphase output signal after passing through the switch 109. Meanwhile, the antiphase input terminal 111 is connected to the gate of the input transistor 101 via the switch 106. An input signal inputted via the antiphase input terminal 111 is outputted, by a function of the load resistor 104 connected to the drain of the input transistor 101, via the in-phase output terminal 112 as an in-phase output signal after passing through the switch 108. That is, the in-phase input signal is amplified by the input transistor 102 and the load resistor 105, whereas the antiphase input signal is amplified by the input transistor 101 and the load resistor 104.
As described above, an amplifier circuit for the in-phase input signal and an amplifier circuit for the antiphase input signal are used by being completely replaced with each other in the states illustrated in FIGS. 24 and 25.
Note here that the following description discusses, with reference to FIGS. 26 and 27, a case where there exists a difference in characteristic, which difference incidentally occurs due to, for example, a manufacturing variation, between the input transistors 101 and 102 and/or between the load resistors 104 and 105, which constitute the differential amplifier circuit.
In a case where a difference occurs between two elements of the differential amplifier circuit which are supposed to have an identical characteristic, an output voltage is in a state deviating from an ideal state, so that the differential amplifier circuit has an offset voltage. Such deviation can be modeled assuming that one of the input terminals is connected to a constant voltage source. FIGS. 26 and 27 each illustrate a state of the modeling. The reference numeral 115 in each of FIGS. 26 and 27 indicates a constant voltage source which models the offset voltage of the differential amplifier circuit. Note that switching elements illustrated in FIG. 26 are identical in state to those illustrated in FIG. 24 and that switching elements illustrated in FIG. 27 are in identical in state to those illustrated in FIG. 25.
In FIG. 26, the constant voltage source 115 is connected to the antiphase input terminal 111 via the switch 107. Meanwhile, in FIG. 27, the constant voltage source 115 is connected to the in-phase input terminal 110 via the switch 107. With this configuration, since the differential amplifier circuit uses the switches 106 through 109, it is possible to change states in which offset voltages of the differential amplifier circuit which are incidentally produced due to a variation are inputted via the antiphase input terminal 111 and the in-phase input terminal 110, respectively. In these two states, the offset voltages across the in-phase output terminal 110 and the antiphase output terminal 111, respectively, are counter in sign and identical in absolute value to each other.
With the above configuration, even if an operational amplifier has an offset voltage which is incidentally produced due to, for example, a manufacturing variation, deviations from respective expectation voltages are equal to each other between a case where a positive-polarity offset voltage is outputted and a case where a negative-polarity offset voltage is outputted. Therefore, no component of a difference between the two deviations remains as an error voltage in an average voltage of driving voltages which are to be applied to liquid crystal display pixels. Accordingly, in a case where the above operational amplifier is used in a liquid crystal drive circuit, there occurs no difference in applied voltage between pixels of a liquid crystal display device, so that display unevenness can be prevented.
FIG. 28 shows a case of the differential amplifier circuit in which P-channel MOS transistors are used as the input transistors.
The reference numerals in FIG. 28 indicate respective members as below. The reference numerals 601 and 602 each indicate a P-channel MOS input transistor. The reference numeral 603 indicates a constant current source that supplies an operational electric current to the differential amplifier circuit. The reference numeral 604 indicates a load resistor (resistance element) of the input transistor 601. The reference numeral 605 indicates a load resistor (resistance element) of the input transistor 602. The reference numerals 606 and 607 each indicate a switch for switching an input signal. The reference numerals 608 and 609 each indicate a switch for switching an output signal. The reference numeral 610 indicates an in-phase input terminal. The reference numeral 611 indicates an antiphase input terminal. The reference numeral 612 indicates an in-phase output terminal. The reference numeral 613 indicates an antiphase output terminal. The reference numeral 614 indicates a switching signal input terminal via which a switching signal for simultaneously switching the switches 606 to 609 is inputted.
The input transistor 601, the load resistor 604, the input transistor 602, and the load resistor 605 constitute an amplifier circuit. The transistors 601 and 602 constitute a differential pair. The switches 606 to 609 are simultaneously controlled by the switching signal 614. Note that the in-phase input terminal 610 corresponds to a + input terminal of the operational amplifier 4602 illustrated in FIG. 21 and that the antiphase input terminal 611 corresponds to a − input terminal of the operational amplifier 4602 illustrated in FIG. 21.
FIG. 29 illustrates a state in which the differential amplifier circuit illustrated in FIG. 28 operates. FIG. 30 illustrates another state in which the differential amplifier circuit illustrated in FIG. 28 operates. The following description discusses, with reference to FIGS. 29 and 30, how the differential amplifier circuit operates.
In the state illustrated in FIG. 29, the in-phase input terminal 610 is connected to a gate of the input transistor 601 via the switch 606. An input signal inputted via the in-phase input terminal 610 is outputted, by a function of the load resistor 604 connected to a drain of the input transistor 601, via the antiphase output terminal 613 as an antiphase output signal after passing through the switch 609. Meanwhile, the antiphase input terminal 611 is connected to a gate of the input transistor 602 via the switch 607. An input signal inputted via the antiphase input terminal 611 is outputted, by a function of the load resistor 605 connected to a drain of the input transistor 602, via the in-phase output terminal 612 as an in-phase output signal after passing through the switch 608. That is, the in-phase input signal is amplified by the input transistor 601 and the load resistor 604, whereas the antiphase input signal is amplified by the input transistor 602 and the load resistor 605.
In contrast, in the state illustrated in FIG. 30, the in-phase input terminal 610 is connected to the gate of the input transistor 602 via the switch 607. An input signal inputted via the in-phase input terminal 610 is outputted, by a function of the load resistor 605 connected to the drain of the input transistor 602, via the antiphase output terminal 613 as an antiphase output signal after passing through the switch 609. Meanwhile, the antiphase input terminal 611 is connected to the gate of the input transistor 601 via the switch 606. An input signal inputted via the antiphase input terminal 611 is outputted, by a function of the load resistor 604 connected to the drain of the input transistor 601, via the in-phase output terminal 612 as an in-phase output signal after passing through the switch 608. That is, the in-phase input signal is amplified by the input transistor 602 and the load resistor 605, whereas the antiphase input signal is amplified by the input transistor 601 and the load resistor 604.
As described above, an amplifier circuit for the in-phase input signal and an amplifier circuit for the antiphase input signal are used by being completely replaced with each other in the states illustrated in FIGS. 29 and 30.
Note here that the following description discusses, with reference to FIGS. 31 and 32, a case where there exists a difference in characteristic, which difference incidentally occurs due to, for example, a manufacturing variation, between the input transistors 601 and 602 and/or between the load resistors 604 and 605, which constitute the differential amplifier circuit.
In a case where a difference occurs between two elements of the differential amplifier circuit which are supposed to have an identical characteristic, an output voltage is in a state deviating from an ideal state, so that the differential amplifier circuit has an offset voltage. Such deviation can be modeled assuming that one of the input terminals is connected to a constant voltage source. FIGS. 31 and 32 each illustrate a state of the modeling. The reference numeral 615 in each of FIGS. 31 and 32 indicates a constant voltage source which models the offset voltage of the differential amplifier circuit. Note that switching elements illustrated in FIG. 31 are identical in state to those illustrated in FIG. 29 and that switching elements illustrated in FIG. 32 are in identical in state to those illustrated in FIG. 30.
In FIG. 31, the constant voltage source 615 is connected to the antiphase input terminal 611 via the switch 607. Meanwhile, in FIG. 32, the constant voltage source 615 is connected to the in-phase input terminal 610 via the switch 607. With this configuration, since the differential amplifier circuit uses the switches 606 through 609, it is possible to change states in which offset voltages of the differential amplifier circuit which are incidentally produced due to a variation are inputted via the antiphase input terminal 611 and the in-phase input terminal 610, respectively. In these two states, the offset voltages across the in-phase output terminal 610 and the antiphase output terminal 611, respectively, are counter in sign and identical in absolute value to each other.
With this configuration, as is the case described earlier, deviations from respective expectation voltages are equal to each other between a case where a positive-polarity offset voltage is outputted and a case where a negative-polarity offset voltage is outputted. Accordingly, in a case where the above operational amplifier is used in a liquid crystal drive circuit, there occurs no difference in applied voltage between pixels of a liquid crystal display device, so that display unevenness can be prevented.
FIG. 33 illustrates a circuit configuration in which load elements of the differential amplifier circuit of FIG. 23 are replaced with active loads having a current mirror configuration. Note that FIG. 33 illustrates a case where N-channel MOS transistors are used as the input transistors.
The reference numerals in FIG. 33 indicate respective members as below. The reference numerals 1101 and 1102 each indicate an N-channel MOS input transistor. The reference numeral 1103 indicates a constant current source that supplies an operational electric current to the differential amplifier circuit. The reference numeral 1104 indicates a P-channel MOS load transistor which serves as a load on the input transistor 1101. The reference numeral 1105 indicates a P-channel MOS load transistor which serves as a load on the input transistor 1102. The reference numerals 1106 and 1107 each indicate a switch for switching an input signal. The reference numerals 1108 and 1109 each indicate a switch for switching an output signal. The reference numeral 1110 indicates an in-phase input terminal. The reference numeral 1111 indicates an antiphase input terminal. The reference numeral 1112 indicates an in-phase output terminal. The reference numeral 1113 indicates an antiphase output terminal. The reference numeral 1114 indicates a switching signal input terminal via which a switching signal for simultaneously switching the switches 1106 to 1109 is inputted.
The differential amplifier circuit is different from the configuration example (passive load) of FIG. 23 in that the load elements are the active loads having a current mirror configuration made up of transistors. In a state corresponding to that of FIG. 24, an in-phase input signal is amplified by each of the input transistor 1101 and the load transistor 1104, whereas an antiphase input signal is amplified by each of the input transistor 1102 and the load transistor 1105. In contrast, in a state corresponding to that of FIG. 25, an in-phase input signal is amplified by each of the input transistor 1102 and the load transistor 1105, whereas an antiphase input signal is amplified by each of the input transistor 1101 and the load transistor 1104.
In any of the cases, the load transistors 1104 and 1105 have a current mirror configuration. Therefore, even if there is a variation in characteristic between the load transistors, electric currents which flow in the respective load transistors 1104 and 1105 are constantly equal to each other. Therefore, the in-phase input signal and the antiphase input signal are amplified at an identical amplification degree, so that an output waveform in bilateral symmetry is obtained.
As described above, also according to the differential amplifier circuit having the structure illustrated in FIG. 33, an amplifier circuit for the in-phase input signal and an amplifier circuit for the antiphase input signal can be used by being completely replaced with each other.
Furthermore, also in a case where there exists a difference in characteristic, which difference incidentally occurs due to, for example, a manufacturing reason, between the input transistors 1101 and 1102 which constitute the differential amplifier circuit, the differential amplifier circuit of FIG. 33 is identical in structure to the differential amplifier circuit of FIG. 23 (not specifically described). Accordingly, since the differential amplifier circuit uses the switches 1106 through 1109, it is possible to change states in which offset voltages of the differential amplifier circuit which are incidentally produced due to a variation are inputted via the antiphase input terminal 1111 and the in-phase input terminal 1110, respectively. In these two states, the offset voltages across the in-phase output terminal 1110 and the antiphase output terminal 1111, respectively, are counter in sign and identical in absolute value to each other.
With this configuration, as is the case described earlier, deviations from respective expectation voltages are equal to each other between a case where a positive-polarity offset voltage is outputted and a case where a negative-polarity offset voltage is outputted. Accordingly, in a case where the above operational amplifier is used in a liquid crystal drive circuit, there occurs no difference in applied voltage between pixels of a liquid crystal display device, so that display unevenness can be prevented.
FIG. 34 illustrates a circuit configuration in which load elements of the differential amplifier circuit of FIG. 28 are replaced with active loads having a current mirror configuration. Note that FIG. 34 illustrates a case where P-channel MOS transistors are used as the input transistors.
The reference numerals in FIG. 34 indicate respective members as below. The reference numerals 1201 and 1202 each indicate a P-channel MOS input transistor. The reference numeral 1203 indicates a constant current source that supplies an operational electric current to the differential amplifier circuit. The reference numeral 1204 indicates an N-channel MOS load transistor which serves as a load on the input transistor 1201. The reference numeral 1205 indicates an N-channel MOS load transistor which serves as a load on the input transistor 1202. The reference numerals 1206 and 1207 each indicate a switch for switching an input signal. The reference numerals 1208 and 1209 each indicate a switch for switching an output signal. The reference numeral 1210 indicates an in-phase input terminal. The reference numeral 1211 indicates an antiphase input terminal. The reference numeral 1212 indicates an in-phase output terminal. The reference numeral 1213 indicates an antiphase output terminal. The reference numeral 1214 indicates a switching signal input terminal via which a switching signal for simultaneously switching the switches 1206 to 1209 is inputted.
The configuration of FIG. 34 is different from the configuration (passive load) of FIG. 28 in that the load elements are the active loads having a current mirror configuration made up of transistors. In a state corresponding to that of FIG. 29, an in-phase input signal is amplified by each of the input transistor 1201 and the load transistor 1204, whereas an antiphase input signal is amplified by each of the input transistor 1202 and the load resistor 1205. In contrast, in a state corresponding to that of FIG. 30, an in-phase input signal is amplified by each of the input transistor 1202 and the load transistor 1205, whereas an antiphase input signal is amplified by each of the input transistor 1201 and the load transistor 1204.
In any of the cases, the load transistors 1204 and 1205 have a current mirror configuration. Therefore, even if there is a variation in characteristic between the load transistors, electric currents which flow in the respective load transistors 1204 and 1205 are constantly equal to each other. Therefore, the in-phase input signal and the antiphase input signal are amplified at an identical amplification degree, so that an output waveform in bilateral symmetry is obtained.
As described above, also according to the differential amplifier circuit having the structure illustrated in FIG. 34, an amplifier circuit for the in-phase input signal and an amplifier circuit for the antiphase input signal are used by being completely replaced with each other.
Furthermore, also in a case where there exists a difference in characteristic, which difference incidentally occurs due to, for example, a manufacturing reason, between the input transistors 1201 and 1202 which constitute the differential amplifier circuit, the differential amplifier circuit of FIG. 34 is identical in structure to the differential amplifier circuit of FIG. 28 (not specifically described). Accordingly, since the differential amplifier circuit uses the switches 1206 through 1209, it is possible to change states in which offset voltages of the differential amplifier circuit which are incidentally produced due to a variation are inputted via the antiphase input terminal 1211 and the in-phase input terminal 1210, respectively. In these two states, the offset voltages across the in-phase output terminal 1210 and the antiphase output terminal 1211, respectively, are counter in sign and identical in absolute value to each other.
With this configuration, as is the case described earlier, deviations from respective expectation voltages are equal to each other between a case where a positive-polarity offset voltage is outputted and a case where a negative-polarity offset voltage is outputted. Accordingly, in a case where the above operational amplifier is used in a liquid crystal drive circuit, there occurs no difference in applied voltage between pixels of a liquid crystal display device, so that display unevenness can be prevented.
FIG. 35 shows a configuration example in which a differential amplifier circuit 1301 equivalent to the differential amplifier circuit illustrated in FIG. 33, switches, and an output section are embodied. Note that FIG. 35 corresponds to an N-channel MOS input operational amplifier.
The reference numerals in FIG. 35 indicate respective members as below. The reference numeral 1301 indicates the differential amplifier circuit illustrated in FIG. 33. The reference numeral 1302 indicates an in-phase input terminal. The reference numeral 1303 indicates an antiphase input terminal. The reference numerals 1304 and 1305 each indicate a switch switching signal input terminal. The reference numerals 1306 to 1309 each indicate a switch. The reference numerals 1310 to 1313 each indicate a switch. The reference numerals 1314 and 1315 each indicate an N-channel MOS input transistor. The reference numerals 1316 and 1317 each indicate a P-channel MOS load transistor which serves as an active load on an input transistor. The reference numeral 1318 indicates a P-channel MOS output transistor. The reference numeral 1319 indicates an N-channel MOS output transistor. The reference numeral 1320 indicates an output terminal. The reference numeral 1321 indicates a bias voltage input terminal for providing the operational amplifier with an operating point. Note here that a circuit in which the differential amplifier circuit 1301 is replaced with a differential amplifier circuit including the resistor loads of FIG. 23 carries out an operation identical to that described below. Accordingly, a detailed description of the operation is omitted here.
In FIG. 35, the reference numerals 1314 and 1315 each correspond to the switch switching signal input terminal 1114 illustrated in FIG. 33, and the terminals 1304 and 1305 receive signals whose polarities are reversed to each other. The following description discusses, with reference to FIGS. 36 and 37, operations in accordance with an input of the switch switching signal.
In FIG. 35, the input transistors 1314 and 1315 correspond to the input transistors 1101 and 1102, respectively, illustrated in FIG. 33, and the load transistors 1316 and 1317 correspond to the load transistors 1104 and 1105, respectively, illustrated in FIG. 33.
Furthermore, the reference numerals in FIG. 35 correspond to the respective members as below. The reference numerals 1307 and 1309 each correspond to the switch 1106 illustrated in FIG. 33. The reference numerals 1306 and 1308 each correspond to the switch 1107 illustrated in FIG. 33. The reference numerals 1310 and 1313 each correspond to the switch 1108 illustrated in FIG. 33. The reference numerals 1311 and 1312 each correspond to the switch 1109 illustrated in FIG. 33. A transistor 1322 corresponds to the constant current source 1103 illustrated in FIG. 33.
When the switching input signal 1304 receives an L level (low level), the switches 1306, 1307, 1310, and 1311 are turned on since these switches are P-channel MOS transistors (see FIG. 36). In this case, the switches 1308, 1309, 1312 and 1313 are turned off since the switch switching signal input terminal 1305 receives an H level (high level). An in-phase input signal 1302 is supplied to the input transistor 1315 via the switch 1306. An antiphase input signal 1303 is supplied to the input transistor 1314 via the switch 1307. Furthermore, a gate signal is supplied to each of the load transistors 1316 and 1317 via the switch 1310, and the gate signal is supplied to the output transistor 1318 via the switch 1311. In the case of FIG. 36, the in-phase input signal is amplified by a circuit constituted by the transistor 1315 and the load transistor 1317, and the antiphase input signal is amplified by a circuit constituted by the transistor 1314 and the load transistor 1316.
When the switch switching signal input terminal 1305 receives an L level, the switches 1308, 1309, 1312, and 1313 are turned on in FIG. 37. In this case, the switches 1306, 1307, 1310 and 1311 are turned off since the switch switching signal input terminal 1304 receives an H level. In this configuration, an in-phase input signal 1302 is supplied to the input transistor 1314 via the switch 1308. An antiphase input signal 1303 is supplied to the input transistor 1315 via the switch 1309. Furthermore, a gate signal is supplied to each of the load transistors 1316 and 1317 via the switch 1313, and the gate signal is supplied to the output transistor 1318 via the switch 1312. In the case of FIG. 37, the in-phase input signal is amplified by a circuit constituted by the input transistor 1314 and the load transistor 1316, and the antiphase input signal is amplified by a circuit constituted by the input transistor 1315 and the load transistor 1317.
As illustrated in FIGS. 36 and 37, according to the present differential amplifier circuit, it is possible to replace the amplifier circuit for the in-phase input signal and the amplifier circuit for the antiphase input signal with each other by switching the switches 1306 to 1313. According to this, also in a case where offset voltages are incidentally produced in the differential amplifier circuit due to, for example, a manufacturing variation in characteristic, the offset voltages are counter in sign and identical in absolute value to each other in these two states (described earlier). Accordingly, in a case where the switches 1306 to 1313 are switched, offset voltages which vary in the operational amplifier can be counter in sign and identical in absolute value to each other, so that the offset voltages can be canceled. Note that a dotted line in each of FIGS. 36 and 37 indicates a signal flow.
FIG. 38 shows a configuration example in which a differential amplifier circuit 1601 equivalent to the differential amplifier circuit illustrated in FIG. 34, switches, and an output section are embodied. Note that FIG. 38 is a P-channel MOS input operational amplifier.
The reference numerals in FIG. 38 indicate respective members as below. The reference numeral 1602 indicates an in-phase input terminal. The reference numeral 1603 indicates an antiphase input terminal. The reference numerals 1604 and 1605 each indicate a switch switching signal input terminal. The reference numerals 1606 to 1609 each indicate a switch. The reference numerals 1610 to 1613 each indicate a switch. The reference numerals 1614 and 1615 each indicate a P-channel MOS input transistor. The reference numerals 1616 and 1617 each indicate an N-channel MOS load transistor which serves as an active load on an input transistor. The reference numeral 1618 indicates an N-channel MOS output transistor. The reference numeral 1619 indicates a P-channel MOS output transistor. The reference numeral 1620 indicates an output terminal. The reference numeral 1621 indicates a bias voltage input terminal for providing the operational amplifier with an operating point. Note here that a circuit in which the differential amplifier circuit 1601 is replaced with a differential amplifier circuit including the resistor loads described in FIG. 28 carries out an operation identical to that described below. Accordingly, a detailed description of the operation is omitted here.
The reference numerals in FIG. 38 correspond to the respective members as below. The input transistors 1614 and 1615 correspond to the input transistors 1201 and 1202, respectively, illustrated in FIG. 34, and the load transistors 1616 and 1617 correspond to the load transistors 1204 and 1205, respectively, illustrated in FIG. 34. Furthermore, the reference numerals 1607 and 1609 each correspond to the switch 1206 illustrated in FIG. 34. The reference numerals 1606 and 1608 each correspond to the switch 1207 illustrated in FIG. 34. The reference numerals 1610 and 1613 each correspond to the switch 1208 illustrated in FIG. 34. The reference numerals 1611 and 1612 each correspond to the switch 1209 illustrated in FIG. 34. A transistor 1622 corresponds to the constant current source 1203 illustrated in FIG. 34.
When the switch switching signal input terminal 1604 receives an H level (high level), the switches 1606, 1607, 1610, and 1611 are turned on since these switches are N-channel MOS transistors (see FIG. 39). In this case, the switches 1608, 1609, 1612 and 1613 are turned off since the switch switching signal input terminal 1605 receives an L level (low level). An in-phase input signal 1602 is supplied to the input transistor 1615 via the switch 1606. An antiphase input signal 1603 is supplied to the input transistor 1614 via the switch 1607. Furthermore, a gate signal is supplied to each of the load transistors 1616 and 1617 via the switch 1610, and the gate signal is supplied to the output transistor 1618 via the switch 1611. In the case of FIG. 39, the in-phase input signal is amplified by a circuit constituted by the input transistor 1615 and the load transistor 1617, and the antiphase input signal is amplified by a circuit constituted by the input transistor 1614 and the load transistor 1616.
When the switch switching signal input terminal 1605 receives an H level, the switches 1608, 1609, 1612, and 1613 are turned on in FIG. 40. In this case, the switches 1606, 1607, 1610 and 1611 are turned off since the switch switching signal input terminal 1604 receives an L level. In this configuration, an in-phase input signal 1602 is supplied to the input transistor 1614 via the switch 1608. An antiphase input signal 1603 is supplied to the input transistor 1615 via the switch 1609. Furthermore, a gate signal is supplied to each of the load transistors 1616 and 1617 via the switch 1613, and the gate signal is supplied to the output transistor 1618 via the switch 1612. In the case of FIG. 40, the in-phase input signal is amplified by a circuit constituted by the input transistor 1614 and the load transistor 1616, and the antiphase input signal is amplified by a circuit constituted by the input transistor 1615 and the load transistor 1617.
As illustrated in FIGS. 39 and 40, according to the present differential amplifier circuit, it is possible to replace the amplifier circuit for the in-phase input signal and the amplifier circuit for the antiphase input signal with each other by switching the switches 1606 to 1613. According to this, also in a case where offset voltages are incidentally produced in the differential amplifier circuit due to, for example, a manufacturing variation, the offset voltages are counter in sign and identical in absolute value to each other in these two states (described earlier). Accordingly, in a case where the switches 1606 to 1613 are switched, offset voltages which vary in the operational amplifier can be counter in sign and identical in absolute value to each other, so that the offset voltages can be canceled. Note that a dotted line in each of FIGS. 39 and 40 indicates a signal flow.
As described above, according to the third conventional technique, a positive-polarity voltage is supplied from the operational amplifier which uses an N-channel MOS transistor in its input stage, a negative-polarity voltage is supplied from the operational amplifier which uses a P-channel MOS transistor in its input stage, and the positive-polarity and negative-polarity voltages are full-range outputted by being switched by the switching switch. Furthermore, according to the third conventional technique, in a case where the in-phase input signal or the antiphase input signal is switched and supplied as an input signal to a corresponding input terminal (a corresponding one of the in-phase input terminal and antiphase input terminal) of the operational amplifier, in addition to the positive-polarity and negative-polarity voltages described above, new positive-polarity and negative-polarity voltages (obtained by reversing the positive-polarity and negative-polarity voltages described above) are generated by the switching of the input signal. This makes it possible to cancel the deviations A and −A, and B and −B in four frames by switching the deviations in the frames, the deviations A and −A each being caused by the offset voltage produced in the operational amplifier which uses an N-channel MOS transistor, and the deviations B and −B each being caused by the offset voltage produced in the operational amplifier which uses a P-channel MOS transistor (see FIG. 41). The third conventional technique thus makes it possible to prevent display unevenness.